Specification and Verification of Gate-Level VHDL Models
of Synchronous and Asynchronous Circuits

David M. Russinoff


We present a mathematical definition of a hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

Full paper: ps, pdf (appeared in Specification and Validation Methods, edited by Egon Börger, Oxford University Press, 1995 )