The floating-point pre-computation behavior of the ARM architecture is formalized by the functions
We have noted that in the ARM architecture, a pre-computation exception never prevents the return of a value,
and an exception flag is not set unless the corresponding trap enable is clear.
The only other departures from SSE pre-computation exception handling are
in the returned value in the case of a NaN operand and the setting of the denormal flag.
The conditions that may cause an exception flag to be set, or
the operation to be terminated with a QNaN value, or both, prior to an ARM floating-point computation are as follows:
- Denormal operand: If FZ = 1, then the operand is forced to and, unless the format is HP,
IDC is asserted; otherwise, neither of these actions is taken. The setting of other flags is based on the result of
this step. Note that a denormal exception is not suppressed by another exceptional condition; it is possible for two flags to be set.
- SNaN operand: IOC is set. If DN = 1, then the real indefinite QNaN is returned (Definition 5.4.4).
Otherwise, the first SNaN operand is converted to a QNaN and returned. For this purpose, in the case of a fused
, the operands are ordered as , , .
- QNaN operand and no SNaN operand: If DN = 1, then the real indefinite QNaN is returned. Otherwise, the first
NaN operand is returned (with fused multiply-add operands ordered as above),
except that in the case of a fused multiply-add
, if is a QNaN, either or is a zero,
and the other is an infinity, then the undefined operation takes precedence over the QNaN operand and the real indefinite
QNaN is returned.
- Undefined Operation: The conditions are as specified in Section 8.3. IOC is set and the real
indefinite QNaN is returned.
- A division operation with any zero as divisor and any
finite numerical dividend: IDZ is set, but the operation proceeds (resulting in an infinity).