10.1 The ARM Floating-Point Status and Control Register
The FPSCR bits that are relevant to the instructions of interest are named as displayed in
- Bits 4:0 and 7 are the cumulative exception flags for invalid operand (IOC), division by zero (DZC),
overflow (OFC), underflow (UFC), inexact result (IXC), and denormal operand (IDE),
- Bits 12:8 and 15 are the trap enables corresponding to the flags, which
determine whether, in the event of exceptional condition, the flag is set by hardware or
control is passed to a trap handler.
- Bits 23:22 form the rounding control field (RC), which encodes
a rounding mode as displayed in Table 10.1. Note the difference between this encoding and that of
- Bit 24 is the force-to-zero bit (FZ), which, if set, coerces both denormal inputs and (except in the
half-precision case--see Section 10.3) denormal results to . Thus, this bit plays the roles of
both the DAZ and FTZ bits of the SSE MXCSR (Section 8.1).
- Bit 25 is the default NaN bit (DN). If asserted, any NaN result of a instruction
is replaced by the real indefinite QNaN (Definition 5.4.4).