In the context of an iterative multiplication-based algorithm, it
often occurs that the result of a multiplication is used as the
multiplier
in the next iteration. In this case, if the Booth
encoding of
can be derived directly from the redundant
representation produced by the compression tree, then
need not be
computed explicitly and the expensive final step of addition may be
avoided.
In this chapter, we shall assume once again that
is an
-bit
vector, but now the multipler to be encoded is
expressed as a sum of two vectors and two carry bits,
where
In particular,
We define a sequence of coefficients
as follows.
and
and let
and
Then for all
PROOF: Let
Assume that the statement holds for some
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It is not obvious that the
lie within the range required by Theorem 7.1.
PROOF: Let
and let
,
,
, and
be
as specified in Definition 7.3.1. Then
where
We may now apply Theorem 7.1.
where
PROOF: Let
,
,
, and
be
as specified in Definition 7.3.1. Since
,
,
and hence
, i.e.,
in Theorem 7.1. The result
follows from the theorem and Lemmas 7.3.1 and 7.3.2.